(1) Field of the Invention
This invention relates to a method of forming a capacitor plate having a cross section shape similar to the Greek letter psi. The shape of the plate provides expanded surface area and increased capacitance. Hemispherical grain polysilicon is also used to increase the surface area.
(2) Description of the Related Art
U.S. Pat. No. 5,389,568 to Yun describes a DRAM capacitor having a capacitor plate with a peripheral wall and a center post with a hole in the center of the center post. The peripheral wall and center post with a hole in the center provide increased surface area for the capacitor plate.
U.S. Pat. No. 5,571,742 to Jeong describes a DRAM capacitor using interconnected stacked capacitor plates to provide increased surface area for the capacitor.
U.S. Pat. No. 5,554,557 to Koh describes a method of forming capacitors using polysilicon sidewall spacers, or fences, to form the capacitor storage electrode.
Patent Application VIS-86-030, Ser. No. 08/949,469, entitled "A METHOD OF FABRICATING A CAPACITOR STORAGE NODE HAVING A RUGGED-FIN SURFACE," filed, Oct. 14, 1997, and now U.S. Pat. No. 5,759,895, assigned to the same assignee describes a method of forming a capacitor from an amorphous silicon plate attached to a polysilicon stud. The polysilicon stud keeps the capacitor plate above the integrated circuit wafer. A low pressure annealing step is used to roughen the surface of the amorphous silicon plate thereby increasing its surface area.
This invention describes a method of forming a capacitor plate having a cross sectional shape similar to the Greek letter psi. Hemispherical grain polysilicon is also used on the surface of the capacitor plate to further increase the surface area.